Added simulation runner script

README.md

@@ -66,3 +66,11 @@ We should think about if the actual details matter.
 Additionally, we can select what ISA we want and what binary we want to run 
     as a CLI argument to the simple.py script.
 The first is the binary we want to run, and the second is x86 for x86 or arm for ARM.
+
+# 2024-04-15 - Milo
+## Simulation Script
+
+Created a script `run_sim.sh` which will run 4 simulations based on the 
+naming that we use in the build script.
+It takes one argument and runs X86 and ARM sims for vector and no vector tests.
+It saves the results in the format: sim-name-arch-[n]vec.

caches.py

+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+""" Caches with options for a simple gem5 configuration script
+
+This file contains L1 I/D and L2 caches to be used in the simple
+gem5 configuration script. It uses the SimpleOpts wrapper to set up command
+line options from each individual class.
+"""
+
+import m5
+from m5.objects import Cache
+
+# Add the common scripts to our path
+m5.util.addToPath("../../gem5/configs/")
+
+from common import SimpleOpts
+
+# Some specific options for caches
+# For all options see src/mem/cache/BaseCache.py
+
+
+class L1Cache(Cache):
+    """Simple L1 Cache with default values"""
+
+    assoc = 2
+    tag_latency = 2
+    data_latency = 2
+    response_latency = 2
+    mshrs = 4
+    tgts_per_mshr = 20
+
+    def __init__(self, options=None):
+        super().__init__()
+        pass
+
+    def connectBus(self, bus):
+        """Connect this cache to a memory-side bus"""
+        self.mem_side = bus.cpu_side_ports
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU-side port
+        This must be defined in a subclass"""
+        raise NotImplementedError
+
+
+class L1ICache(L1Cache):
+    """Simple L1 instruction cache with default values"""
+
+    # Broadwell and Skylake
+    size = "32kB"
+    assoc = 8
+    tag_latency = 4
+    data_latency = 4
+    response_latency = 4
+
+    SimpleOpts.add_option(
+        "--l1i_size", help=f"L1 instruction cache size. Default: {size}"
+    )
+
+    def __init__(self, opts=None):
+        super().__init__(opts)
+        if not opts or not opts.l1i_size:
+            return
+        self.size = opts.l1i_size
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU icache port"""
+        self.cpu_side = cpu.icache_port
+
+
+class L1DCache(L1Cache):
+    """Simple L1 data cache with default values"""
+
+    # Broadwell and Skylake
+    size = "32kB"
+    assoc = 8
+    tag_latency = 4
+    data_latency = 4
+    response_latency = 4
+
+    SimpleOpts.add_option(
+        "--l1d_size", help=f"L1 data cache size. Default: {size}"
+    )
+
+    def __init__(self, opts=None):
+        super().__init__(opts)
+        if not opts or not opts.l1d_size:
+            return
+        self.size = opts.l1d_size
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU dcache port"""
+        self.cpu_side = cpu.dcache_port
+
+
+class L2Cache(Cache):
+    """Simple L2 Cache with default values"""
+
+    mshrs = 20
+    tgts_per_mshr = 12
+
+    #   Broadwell
+    #size = "256kB"
+    #assoc = 8
+    #tag_latency = 12
+    #data_latency = 12
+    #response_latency = 12
+
+    #   Skylake
+    size = "1024kB"
+    assoc = 16
+    tag_latency = 14
+    data_latency = 14
+    response_latency = 14
+
+    SimpleOpts.add_option("--l2_size", help=f"L2 cache size. Default: {size}")
+
+    def __init__(self, opts=None):
+        super().__init__()
+        if not opts or not opts.l2_size:
+            return
+        self.size = opts.l2_size
+
+    def connectCPUSideBus(self, bus):
+        self.cpu_side = bus.mem_side_ports
+
+    def connectMemSideBus(self, bus):
+        self.mem_side = bus.cpu_side_ports
+
+
+
+class L3Cache(Cache):
+    # size = '1kB'
+    # size = '8192kB'
+    # size = '131072kB'
+    #assoc = 8
+    #tag_latency = 20
+    #data_latency = 20
+    #response_latency = 20
+    mshrs = 20
+    tgts_per_mshr = 20
+
+    # Broadwell
+    #size = "32768kB"
+    #assoc = 8
+    #tag_latency = 50
+    #data_latency = 50
+    #response_latency = 50
+
+    # Skylake
+    size = "16384kB"
+    assoc = 8
+    tag_latency = 50
+    data_latency = 50
+    response_latency = 50
+
+    SimpleOpts.add_option('--l3_size', help="L3 cache size. Default: %s" % size)
+
+    def __init__(self, opts=None):
+        super(L3Cache, self).__init__()
+        if not opts or not opts.l3_size:
+            return
+        self.size = opts.l3_size
+
+    def connectCPUSideBus(self, bus):
+        self.cpu_side = bus.mem_side_ports
+
+    def connectMemSideBus(self, bus):
+        self.mem_side = bus.cpu_side_ports   
+
+
+class L4Cache(Cache):
+    """Simple L4 Cache with default values"""
+
+    # Default parameters
+    size = '2kB'
+    #size = '131072kB'
+    assoc = 16
+    tag_latency = 27
+    data_latency = 27
+    response_latency = 27
+    mshrs = 20
+    tgts_per_mshr = 12
+
+    SimpleOpts.add_option('--l4_size', help="L4 cache size. Default: %s" % size)
+
+    def __init__(self, opts=None):
+        super(L4Cache, self).__init__()
+        if not opts or not opts.l4_size:
+            return
+        self.size = opts.l4_size
+
+    def connectCPUSideBus(self, bus):
+        self.cpu_side = bus.mem_side_ports
+
+    def connectMemSideBus(self, bus):
+        self.mem_side = bus.cpu_side_ports

run_sim.sh

+#!/usr/bin/bash
+HOME="/home/ugrads/majors/miloc"
+GEM5="$HOME/gem5_workspace/gem5"
+echo "Running 4 simulations in parallel"
+
+$GEM5/build/X86/gem5.opt -d sim-$1-x86-nvec simple.py $1-x86-nvec x86 &
+$GEM5/build/X86/gem5.opt -d sim-$1-x86-vec simple.py $1-x86-vec x86 &
+$GEM5/build/ARM/gem5.opt -d sim-$1-arm-nvec simple.py $1-arm-nvec arm &
+$GEM5/build/ARM/gem5.opt -d sim-$1-arm-vec simple.py $1-arm-vec arm &
+
+wait
+echo "Finished simulation :)"
+
+