Improved simple.py for scripting ease

README.md

@@ -62,3 +62,7 @@ One thought is that if we compare the speedup between vectorized and non-vectori
 I copied the given class configuration for the CPU microachitectural details.
 It uses an Intel Skylake style cache hierarchy.
 We should think about if the actual details matter.
+
+Additionally, we can select what ISA we want and what binary we want to run 
+    as a CLI argument to the simple.py script.
+The first is the binary we want to run, and the second is x86 for x86 or arm for ARM.

simple.py

@@ -6,6 +6,27 @@ m5.util.addToPath("../gem5/configs/")
 
 from caches import *
 
+# Add command line options to the script
+from common import SimpleOpts 
+
+thispath = os.path.dirname(os.path.realpath(__file__))
+binary = os.path.join(
+    thispath,
+    #"./matmul.novector",
+    #"./matmul86",
+    #"./nq86",
+    #"./lts86",
+    "./Bubblesort-arm",
+)
+
+def_cpu = "ARM"
+SimpleOpts.add_option("binary", nargs="?", default=binary)
+SimpleOpts.add_option("cpu", nargs="?", default=def_cpu)
+
+
+args = SimpleOpts.parse_args()
+binary = os.path.join(thispath, args.binary)
+print(binary)
 # Create our system
 system = System()
 
@@ -16,11 +37,28 @@ system.clk_domain.voltage_domain = VoltageDomain()
 system.mem_mode = 'timing'
 system.mem_ranges =[AddrRange('8192MB')] # Give plenty of RAM
 
-# Specify what CPU we are running
-#system.cpu = X86TimingSimpleCPU()
-system.cpu = ArmTimingSimpleCPU()
+system.membus = SystemXBar()
 
+if "x" in args.cpu.lower():
+    system.cpu = X86TimingSimpleCPU()
+else:
+    system.cpu = ArmTimingSimpleCPU()
+
+system.cpu.createInterruptController()
 system.membus = SystemXBar()
+# Specify what CPU we are running
+if "x" in args.cpu.lower():
+    print("Simulating x86")
+#    system.cpu = X86TimingSimpleCPU()
+    # x86 only
+    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
+else:
+    print("Simulating ARM")
+#    system.cpu = ArmTimingSimpleCPU()
+    #system.cpu.createInterruptController()
+
 
 # Instantiate L1 instruction and data caches
 system.cpu.icache = L1ICache()
@@ -48,18 +86,9 @@ system.l2cache.connectMemSideBus(system.l3bus)
 system.l3cache = L3Cache()
 system.l3cache.connectCPUSideBus(system.l3bus)
 
-system.membus = SystemXBar()
 
 system.l3cache.connectMemSideBus(system.membus)
 
-
-system.cpu.createInterruptController()
-
-# x86 only
-#system.cpu.interrupts[0].pio = system.membus.mem_side_ports
-#system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
-#system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
-
 system.system_port = system.membus.cpu_side_ports
 
 system.mem_ctrl = MemCtrl()
@@ -67,15 +96,6 @@ system.mem_ctrl.dram = DDR3_1600_8x8()
 system.mem_ctrl.dram.range = system.mem_ranges[0]
 system.mem_ctrl.port = system.membus.mem_side_ports
 
-thispath = os.path.dirname(os.path.realpath(__file__))
-binary = os.path.join(
-    thispath,
-    #"./matmul.novector",
-    #"./matmul86",
-    #"./nq86",
-    #"./lts86",
-    "./Bubblesort-arm",
-)
 system.workload = SEWorkload.init_compatible(binary)
 
 process = Process()